The subject application is related to subject matter disclosed in Japanese Patent Application No. 2000-66689 filed on Mar. 10, 2000 in Japan to which the subject application claims priority under Paris Convention and which is incorporated herein by reference.
This invention relates to a ferroelectric memory (hereinafter sometimes referred to as FeRAM), and more particularly to performance assurance of a ferroelectric memory used in a destructive reading mode.
As a ferroelectric memory, there is known one having a combination of a ferroelectric capacitor and a transistor to form a ferroelectric memory cell that can be electrically rewritable. This type of ferroelectric memory is capable of nonvolatile storage of data by using a hysteresis characteristic of the ferroelectric capacitor. That is, it is similar to EEPROM in capability of holding data even after the power supply is interrupted, and its application to various kinds of IC cards and portable terminals, for example.
With such a ferromagnetic memory, however, unlike EEPROM, data reading is destructive reading. That is, when data is read out, one of xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d is accompanied by spontaneous polarization reversal, and rewriting is indispensable. This means that stored data is destructed upon interruption of the power supply or a decrease of the voltage below an operation assurance voltage during data reading or other operation.
The conventional ferroelectric memory is not assisted by any operation assurance against accidental interruption of the power supply, for example, during operation.
It is therefore an object of the invention to provide a ferroelectric memory with operation assurance against a drop of the power supply during operation.
According to one aspect of the present invention, there is provided a ferroelectric memory having:
a memory cell array of memory cells having ferroelectric capacitors, which is divided into a plurality of blocks:
a boost power circuit provided in each said block of said memory cell array to generate a boost voltage required for operation of the memory;
a boost power switch provided between a power line connected to an external power terminal and a power supply terminal of each said boost power circuit, and remaining ON during normal operation of the memory;
a voltage detector circuit for detecting a drop of voltage level of said power line; and
a switch control circuit for turning off said boost power switches in said blocks of said memory cell array excluding the boost power switch in a currently selected block in response to said voltage detector circuit.
According to another aspect of the present invention, there is provided a ferroelectric memory having:
a memory cell array of memory cells having ferroelectric capacitors, which is divided into a plurality of blocks:
a first power switch of normally closed type connected to an external power terminal;
a power line, one end thereof being connected to said first power switch and the other end thereof being grounded via a first power capacitor;
a boost power circuit connected to said power line and provided in each said block of said memory cell array to generate a boost voltage required for operation of the memory;
a second power switch of normally open type connected in parallel to said boost power circuit and provided in each said block of said memory cell array;
a voltage detector circuit for detecting a drop of voltage level of said power line; and
a switch control circuit for turning on said second power switches in said blocks of said memory cell array excluding the second power switch in a currently selected block in response to said voltage detector circuit.
According to the invention, when the voltage value decreases below an operation assurance voltage in a boost power circuit provided in each block of a memory array and normally supplied with a power supply, the source voltage of a selected block is enhanced or compensated by turning off the power switches of boost power circuits excluding the boost power circuit of a currently selected block and thereby supplying an external source voltage only to the boost power circuit of the selected block (supplying the voltage held in the power line capacitor only to the boost power circuit of the selected block even when the external power supply is interrupted). Thereby, destruction of stored data in the selected block can be prevented.